The Number That Defined an Industry
In 1965, Gordon Moore scribbled a prediction on a napkin that would define the trajectory of human civilization: the number of transistors on a microchip would double roughly every two years. For nearly six decades, Moore’s Law held — not as a law of physics, but as a self-fulfilling prophecy. Engineers at Intel, AMD, and later TSMC and Samsung organized their entire R&D roadmaps around it. If you failed to double transistor density on schedule, your competitor wouldn’t.
But physics, unlike venture capital, doesn’t negotiate. We’re now building transistors so small that individual atoms matter. The race to the 1-nanometre node — a marketing term, yes, but one that captures a genuine engineering precipice — has become the semiconductor industry’s defining challenge. The question isn’t just whether we can build a 1nm chip. It’s whether the economic and physical foundations of the entire industry survive the attempt.
Where We Actually Are: The State of Advanced Nodes in 2025
Let’s be clear about what “nanometres” mean today. TSMC’s N3 node (their “3nm” process), which powers the A17 Pro in the iPhone 15 Pro and Apple’s M3 chips, doesn’t actually have any features measuring 3 nanometres. The naming convention long ago detached from physical dimensions. What matters is transistor density. TSMC’s N3 delivers roughly 190-200 million transistors per square millimetre, up from about 135 million on N5. That’s real progress, but the slope is flattening.
TSMC began risk production on its N2 (2nm) node in 2024, with volume production expected in late 2025 or early 2026. N2 introduces gate-all-around (GAA) transistors — TSMC calls them “nanosheet” transistors — replacing the FinFET architecture that has dominated since Intel introduced it in 2011. Samsung beat TSMC to GAA with its 3nm node in 2022, though yields have been famously problematic. Intel, under its ambitious “five nodes in four years” plan, expects its 18A node (roughly equivalent to 1.8nm) to be manufacturing-ready in 2025.
So where does that leave 1 nanometre? The IEEE International Roadmap for Devices and Systems (IRDS) projects that “1nm equivalent” nodes won’t enter production until 2029 or later. Between now and then, the industry needs to solve several problems that don’t have obvious solutions.
The Physics Problem: Atoms Don’t Scale
At around 1nm — or whichever marketing term we assign to transistor channels roughly 10-12 atoms wide — quantum tunneling becomes the dominant failure mode. Electrons start teleporting through barriers they shouldn’t cross, turning your carefully engineered transistor from a switch into a leaky pipe. Gate oxides, the insulating layers that control current flow, are already just a handful of atoms thick. Make them thinner and leakage current explodes. Make them thicker and you lose control over the channel.
“We’re approaching fundamental limits,” Dr. Chenming Hu, the inventor of the FinFET transistor, told the IEEE in 2024. “At some point, you simply run out of atoms.” The semiconductor industry has been hearing this warning for thirty years and has always found a way around it — strained silicon, high-k metal gates, FinFETs, EUV lithography. But each solution has been harder and more expensive than the last.
The power problem may actually be worse than the size problem. As transistors shrink, power density increases. Dennard scaling — the observation that power density stays constant as transistors shrink — broke down around 2006. Since then, we’ve been cramming more transistors onto chips that can’t fully utilize them simultaneously without melting. Modern server CPUs already leave significant portions of the die “dark” at any given moment to manage thermals.
The ASML Bottleneck: One Company, One Machine, One Future
If there’s a single point of failure in the semiconductor roadmap, it’s ASML. The Dutch company holds a monopoly on extreme ultraviolet (EUV) lithography, the technology required for features below about 7nm. ASML’s Twinscan NXE:3800E systems, each weighing 180 tonnes and costing roughly $200 million, fire 50,000 droplets of tin per second with a laser, creating plasma that emits 13.5nm wavelength light — light so finicky it gets absorbed by air, requiring the entire optical path to operate in a vacuum.
ASML’s High-NA EUV machines (the EXE:5200), which began shipping in 2024, push numerical aperture from 0.33 to 0.55, enabling even finer resolution. Each one costs an estimated $380 million. Intel was first in line, taking delivery of the initial systems. TSMC and Samsung have been more measured, partly because High-NA EUV requires new mask infrastructure and partly because each machine draws roughly 1.4 megawatts — the power consumption of a small town.
The economics here are staggering. A modern fab costs $20-30 billion. A single High-NA EUV scanner costs nearly $400 million. Only three companies on Earth — TSMC, Samsung, and Intel — can afford to play at this level. The consolidation of leading-edge manufacturing into essentially one company (TSMC, with roughly 90% market share in advanced nodes) creates geopolitical fragility that has governments from Washington to Berlin to Tokyo losing sleep.
Beyond Silicon: The Post-CMOS Future
The 1nm barrier may force the industry to abandon silicon entirely. Researchers are exploring several alternatives:
2D materials: Transition metal dichalcogenides like molybdenum disulfide (MoS₂) can form stable layers just one atom thick, potentially enabling transistors with channel lengths below 1nm. In 2022, researchers at MIT and TSMC demonstrated a MoS₂ transistor with a gate length of approximately 0.34nm — essentially a single carbon atom wide. The catch? Manufacturing MoS₂ at wafer scale remains a lab experiment, not an industrial process.
Carbon nanotubes: CNTFETs (carbon nanotube field-effect transistors) have shown promise for decades. In 2019, a team at MIT built a working 16-bit microprocessor from 14,000 CNTFETs. But purifying and aligning nanotubes at commercial scale has proven extraordinarily difficult.
Photonic and neuromorphic computing: Some researchers argue the path forward isn’t smaller transistors but fundamentally different computing paradigms — chips that compute with light instead of electrons, or that mimic the brain’s architecture. This doesn’t extend Moore’s Law so much as change the game entirely.
What This Means for the Rest of Us
The end of transistor scaling doesn’t mean the end of computing progress — but it does mean progress will look different. The gains will come from architecture (Apple’s M-series chips already demonstrate what’s possible with better design, not just smaller transistors), from specialized accelerators (GPUs, NPUs, and custom silicon), from better software, and from packaging innovations like chiplet architectures that let designers mix and match different process nodes.
AMD’s chiplet approach with Ryzen and EPYC processors has shown that you don’t need a monolithic die on the most advanced node to deliver competitive performance. Intel’s Meteor Lake uses four different process nodes in a single package. This disaggregation strategy may keep the spirit of Moore’s Law alive even after the literal transistor doubling stops.
The 1nm milestone, whenever we reach it, will probably be more symbolic than practical. The real story is that we’ve spent sixty years getting here, and the easy gains are behind us. Nobody’s throwing in the towel — TSMC, Samsung, and Intel collectively spend over $100 billion a year on R&D and capital expenditure. But we’re entering an era where progress will be measured in architectural cleverness and manufacturing yield, not just smaller numbers on a marketing slide.
Moore’s Law, in the end, was never a law. It was a challenge. And the industry is taking it.
The Money Problem: Who Pays for the Frontier?
The unit economics of leading-edge semiconductors have become genuinely frightening. When Intel built its Fab 42 in Arizona, the price tag was around $7 billion for a single factory. TSMC’s Arizona facilities, announced in stages beginning in 2020, now involve a commitment exceeding $65 billion for three fabs — the largest foreign direct investment in a single project in US history. The subsidies involved are equally unprecedented: the US CHIPS and Science Act of 2022 allocated $39 billion in direct manufacturing incentives, while the European Chips Act committed €43 billion, and Japan has pledged over ¥3 trillion to rebuild its semiconductor industry.
This is the legacy of decades of wafer-thin margins and brutal capital intensity. In the 1980s, more than two dozen companies built leading-edge fabs. By the 2010s, that number had collapsed to a handful. By 2025, effectively three — TSMC, Samsung, and Intel — with Intel struggling to regain competitiveness after years of process node delays.
The concentration creates a paradox. The world needs more advanced semiconductor manufacturing capacity to reduce geopolitical risk, but the economics make further consolidation almost inevitable. Building a redundant, independent leading-edge fab ecosystem would cost trillions of dollars — money that neither private markets nor governments have shown a full willingness to commit.
What the 1nm Node Will Actually Look Like
When it arrives — probably around 2030 if current roadmaps hold — the “1nm” node will look very different from what the label suggests. It will almost certainly use gate-all-around transistors (already arriving at 2nm), stacked nanosheets, and backside power delivery — a technique Intel is pioneering that routes power through the back of the wafer rather than the front, freeing up space for signal routing and reducing resistance. It may also use complementary FETs (CFETs), which stack the n-type and p-type transistors vertically instead of side by side, effectively doubling density.
Beyond that, the horizon gets murkier. 2D materials, carbon nanotubes, and vertical nanowires all remain candidates, but none has yet demonstrated manufacturability at scale. What’s clear is that the era of “just shrink the transistor” is ending, and the era of “fundamentally rethink the transistor” is beginning. The companies and countries that win that transition won’t just dominate computing — they’ll define it.
