Gordon Moore’s famous observation — that the number of transistors on a microchip doubles roughly every two years — has held up with astonishing fidelity since 1965. But physics is not negotiable. Silicon atoms are roughly 0.2 nanometres apart. As transistor gates approach the size of a few dozen atoms, quantum tunnelling — electrons leaking through barriers that classical physics says should block them — becomes impossible to ignore. The industry is now talking about one-nanometre chips. The question is whether they are achievable, and what they will cost.
Where We Are Now
As of 2025, the most advanced commercially available chips use TSMC’s 3-nanometre process (N3), which powers Apple’s A17 Pro and M3 chips, as well as a growing share of Qualcomm, AMD and Intel processors. TSMC’s 3nm process packs roughly 190 million transistors per square millimetre — more than triple the density of its 7nm process from 2018. The company’s 2nm process (N2), expected to enter risk production in 2025 and volume production in 2026, will use gate-all-around (GAA) transistors — a fundamentally different transistor architecture that wraps the gate around the channel on all four sides, dramatically reducing leakage current compared with the FinFET transistors used in every process from 16nm through 3nm. TSMC claims N2 will deliver 10-15% higher performance at the same power, or 25-30% lower power at the same performance, compared with N3. Samsung, which has been shipping GAA transistors in its 3nm process since 2022, has struggled with yield rates — the percentage of functional chips per wafer — reportedly below 60%, compared with TSMC’s N3 yields estimated around 80%. Low yields make the economics of advanced chip production punishing: each wafer processed through a cutting-edge fab costs roughly $20,000, and if only half the chips work, the cost per functional chip doubles.
Intel, after a decade of manufacturing stumbles, is pursuing an aggressive roadmap under CEO Pat Gelsinger. The company’s 18A process (equivalent to 1.8nm), using its own GAA implementation called RibbonFET, is scheduled for production readiness in 2025. If Intel can execute — and that is a significant ‘if’ given its history of delays — it would leapfrog TSMC and Samsung to the process lead for the first time in nearly a decade. The US CHIPS Act, which is providing Intel with up to $8.5 billion in direct funding, has made this bet a matter of national industrial policy as much as corporate strategy.
The Toolmaker That Makes Everything Possible
Every advanced chip in the world is made using lithography machines built by a single company: ASML, headquartered in Veldhoven, the Netherlands. ASML’s extreme ultraviolet (EUV) lithography systems, which use 13.5-nanometre wavelength light to etch features far smaller than traditional optics allow, are the most complex machines ever built for industrial production. A single EUV system costs approximately $200 million, weighs 180 tonnes and requires three Boeing 747 cargo planes to transport. ASML shipped only 42 EUV systems in 2023 and expects to increase that to roughly 60 by 2025, essentially capping the total number of cutting-edge chips the world can produce each year.
The next frontier — high-NA EUV — uses a larger numerical aperture to achieve even finer resolution. ASML shipped its first high-NA EUV system, the EXE:5000, to Intel in early 2024. TSMC and Samsung will follow. Each high-NA system costs approximately $380 million and is required for processes at 2nm and below. The physics of scaling is pushing every lever — transistor architecture, lithography wavelength, numerical aperture, materials science — simultaneously. This is why Moore’s Law has lasted as long as it has: the industry has repeatedly found new knobs to turn just as the previous ones ran out of range. But the number of available knobs is finite, and each one costs exponentially more than the last.
Beyond Silicon
The successor to the silicon transistor is likely to be something entirely different: complementary field-effect transistors (CFETs) that stack n-type and p-type transistors vertically, two-dimensional materials like molybdenum disulfide that can be deposited in layers just a few atoms thick, and eventually spintronic or photonic devices that use electron spin or light rather than charge to carry information. These are not science fiction — research groups at TSMC, Intel, IBM and IMEC are actively working on all of them — but they are a decade or more from commercial viability. In the meantime, the industry is pursuing a strategy known as ‘More than Moore’: improving performance not by shrinking transistors but by packaging them more cleverly. Chiplet architectures, advanced 3D stacking, and heterogeneous integration — putting logic, memory and specialised accelerators on a single package — are delivering performance improvements even as transistor scaling slows. The semiconductor industry has survived every prediction of its demise for six decades. The bets it is placing now suggest it intends to survive for at least one more.
